Patent · US Active

Semiconductor device having a planar III-N semiconductor layer and fabrication method

US11862459B2 · kind B2 · utility

0Cited by

8References

4Claims

0Family size

Assignee

HEXAGEM AB · SE

Inventors

Jonas Ohlsson · Malmö, SE
Lars Samuelson · Malmö, SE
Kristian Storm · Hjärup, SE
Rafal Ciechonski · Lund, SE
Bart Markus · Hjärup, SE

Key dates

Filing date	Jun 20, 2022
Grant date	Jan 2, 2024
Priority date	—
Expiry date	Jun 20, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/817
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device having a planar III-N semiconductor layer includes a substrate including a wafer and a buffer layer of a buffer material different from a material of the wafer, the buffer layer having a growth surface, an array of nanostructures epitaxially grown from the growth surface, a continuous planar layer formed by coalescence of upper parts of the nanostructures at an elevated temperature T, where the number of lattice cells spanning a center distance between adjacent nanostructures are different at the growth surface and at the coalesced planar layer, and a growth layer epitaxially grown on the planar layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.