Seal ring designs supporting efficient die to die routing
US11862481B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Mar 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.