Display panel, array substrate, and manufacturing method thereof
US11862642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2020 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.