Devices and methods for compact radiation-hardened integrated circuits

US11862724B1 · kind B1 · utility

Assignee

• Apogee Semiconductor, Inc. · US

Inventor

• Mark Hamlyn · Sachse, US

Key dates

• Filing date: Sep 1, 2023
• Grant date: Jan 2, 2024
• Expiry date: Sep 1, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes. These designs and processes allow a mix of integrated circuits having differing levels of tolerance to total ionizing dose on the same semiconductor wafer.