Three-dimensional semiconductor memory device
US11864385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.