Method for fabricating displaying backplane, displaying backplane and displaying device
US11864422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | May 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for fabricating a displaying backplane, a displaying backplane and a displaying device, and relates to the technical field of displaying. The method includes forming a first active layer and a second active layer on a substrate base plate; forming a first grid insulating layer covering the first active layer and the second active layer; forming a first grid on the first grid insulating layer; performing ion implantation to the first no-channel regions, the second no-channel regions and the second channel region, to reduce oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region; and forming a second grid on the first grid insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.