Adaptive clock signal frequency scaling
US11868194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jun 14, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.