Systems and methods for processing asynchronous reset events while maintaining persistent memory state
US11868265B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Mar 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.