Hardware implementation of convolutional layer of deep neural network
US11868426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Nov 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware implementations of, and methods for processing, a convolution layer of a DNN that comprise a plurality of convolution engines wherein the input data and weights are provided to the convolution engines in an order that allows input data and weights read from memory to be used in at least two filter-window calculations performed either by the same convolution engine in successive cycles or by different convolution engines in the same cycle. For example, in some hardware implementations of a convolution layer the convolution engines are configured to process the same weights but different input data each cycle, but the input data for each convolution engine remains the same for at least two cycles so that the convolution engines use the same input data in at least two consecutive cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.