Direct memory access operation for neural network accelerator
US11868872B1 · kind B1 · utility
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Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | May 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, an apparatus comprises: a direct memory access (DMA) descriptor queue that stores DMA descriptors, each DMA descriptor including an indirect address; an address translation table that stores an address mapping between indirect addresses and physical addresses; and a DMA engine configured to: fetch a DMA descriptor from the DMA descriptor queue to the address translation table to translate a first indirect address of the DMA descriptor to a first physical address based on the address mapping, and perform a DMA operation based on executing the DMA descriptor to transfer data to or from the first physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.