Storage device
US11869610B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Aug 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes a storage circuit, a reading circuit, a first check circuit, and a second check circuit. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays which are arranged alternately. A first data wire is electrically connected to each of the sense amplifier arrays. The reading circuit is configured to read data on the first data wire. Both the first check circuit and the second check circuit are electrically connected to the reading circuit. The reading circuit is configured to transmit a part of the read data to the first check circuit for error checking and/or correcting, and transmit another part of the read data to the second check circuit for error checking and/or correcting. The data transmitted to the first check circuit and the data transmitted to the second check circuit are respectively from adjacent sense amplifier arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.