Semiconductor package with improved board level reliability
US11869831B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Dec 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48175
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.