Storage device generating multi-level chip enable signal and operating method thereof
US11869860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.