Power electronics heat removal
US11869881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2023 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Mar 2, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T50/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power electronics converter includes a multi-layer planar carrier substrate having a plurality of electrically conductive layers, at least one electrical connection, and a converter commutation cell comprising a power circuit and a gate driver circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is included in a power semiconductor prepackage having one or more power semiconductor switching elements embedded in a solid insulating material. The power electronics converter includes a heat sink configured to remove heat from the power semiconductor prepackage. A converter parameter η is greater than or 20 equal to 100 kW/m3K, η being defined as a heat transfer coefficient between the heat removal side of the power semiconductor prepackage and a cooling medium of the heat sink divided by the size of a gap between the power semiconductor prepackage and the heat sink.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.