Control gate strap layout to improve a word line etch process window
US11869951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.