Summing circuit and equalizer including the same
US11870615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jul 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.