Circuit and method for image artifact reduction in high-density, high-pixel-count, image sensor with phase detection autofocus
US11871135B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Feb 3, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | May 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/134
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.