Mechanism of enabling fault handling with PCIE re-timer
US11874724B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jan 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An extension device is positioned within a point-to-point link to connect two devices, where the extension device includes error detection circuitry to detect a set of errors at the extension device. The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. The extension device further includes a transmitter to transmit a notification signal to indicate the detection of the error and presence of data in the evert register associated with the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.