Cluster interlayer safety mechanism in an artificial neural network processor
US11874900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Nov 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Novel and useful system and methods of functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The NN processor incorporates functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.