Systems and methods for stalling host processor
US11875180B2 · kind B2 · utility
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140References
25Claims
0Family size
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Key dates
| Filing date | Aug 3, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Aug 3, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/75
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.