Shift register, gate driving circuit and display panel
US11875715B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jul 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub-circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit performs noise reduction on the first signal output terminal by the non-operation level signal during the blank period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.