Display driving circuit and display device including the same
US11875761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Sep 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display driving circuit includes a frame rate extractor configured to receive a vertical synchronization signal indicating a start of a k-th frame, k-th frame data including information about the k-th frame, and a data enable signal indicating an active period of the k-th frame and a variable blank period that occurs after the active period, and extract a frame rate of the k-th frame, based on the vertical synchronization signal; and an image corrector configured to correct frame data received after reception of the k-th frame data, based on the frame rate of the k-th frame, and output the corrected frame data as output image data, wherein the vertical synchronization signal is received before a start time point of the active period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.