Static random access memory device
US11875844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jul 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.