Mitigating edge layer effect in partially written blocks
US11875864B2 · kind B2 · utility
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5References
14Claims
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Key dates
| Filing date | Oct 12, 2021 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Oct 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.