Method of forming integrated circuit package
US11876026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Feb 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a glass core layer, where the glass core layer includes a first major surface, a second major surface, and a cavity disposed between the first major surface and the second major surface of the glass core layer. The package also includes a die disposed in the cavity of the glass core layer, an encapsulant disposed in the cavity between the die and a sidewall of the cavity, a first patterned conductive layer disposed adjacent the first major surface of the glass core layer, and a second patterned conductive layer disposed adjacent the second major surface of the glass core layer. The die is electrically connected to at least one of the first and second patterned conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.