Package with a substrate comprising an embedded capacitor with side wall coupling
US11876085B2 · kind B2 · utility
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2References
19Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first interconnect and a second interconnect, a capacitor located at least partially in the substrate, the capacitor comprising a first terminal and a second terminal, a first solder interconnect coupled to a first side surface of the first terminal and the first interconnect, and a second solder interconnect coupled to a second side surface of the second terminal and the second interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.