Resistive memory array with localized reference cells
US11881241B2 · kind B2 · utility
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Key dates
| Filing date | Mar 31, 2022 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.