Semiconductor memory device
US11881267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.