Semiconductor storage device
US11881273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jul 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.