Multiplexing sample-and-hold circuit
US11881851B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jan 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.