Superconducting integrated circuit design method based on placement and routing by different-layer JTLs

US11881855B2 · kind B2 · utility

Assignee

• SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Jie Ren · Lo Wu, CN
• Ruo Ting Yang · Shanghai, CN
• Xiao Gao · Shanghai, CN
• Zhen Wang · Dongguan, CN

Key dates

• Filing date: Mar 22, 2021
• Grant date: Jan 23, 2024
• Expiry date: Sep 27, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N69/00
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.