Interface bus combining
US11886228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jun 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.