Apparatus and methods for burst communications within die architectures
US11886369B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2023 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Sep 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.