Memory circuit for storing parsimonious data
US11886719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Aug 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit for storing parsimonious data and intended to receive an input vector of size Iz, includes an encoder, a memory block comprising a first memory region and a second memory region divided into a number Iz of FIFO memories, each FIFO memory being associated with one component of the input vector, only non-zero data being saved in the FIFO memories, a decoder, the encoder being configured to generate an indicator of non-zero data for each component of the input vector, the memory circuit being configured to write the non-zero data of the input data vector to the respective FIFO memories and to write the indicator of non-zero data to the first memory region, the decoder being configured to read the outputs of the FIFO memories and the associated indicator in the first memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.