Hybrid analog-digital matrix processors
US11886942B2 · kind B2 · utility
2Cited by
61References
18Claims
0Family size
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Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Dec 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
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