Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions
US11886981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2020 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jul 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.