Shift register, gate drive circuit and drive method thereof
US11887554B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 19, 2020 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Feb 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.