Time-interleaving sensing scheme for pseudo dual-port memory
US11887660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Aug 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a pseudo dual-port memory. The pseudo dual-port memory includes a single-port memory, a multiplexer, a timing control circuit and an output circuit. The multiplexer is configured to sequentially output a first address and a second address to the single-port memory. The output circuit is configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address. The output circuit includes a first sense amplifier and a second sense amplifier, wherein the first sense amplifier receives the output data to generate first data serving as the first reading result according to a first control signal, and the second sense amplifier receives the output data to generate second data serving as the second reading result according to a second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.