Low latency network device and method for treating received serial data
US11888586B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jun 15, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jul 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/24
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A low-latency network device and method for treating serial data comprising an oscillator generating a device-wide clock; a receiving physical medium attachment (PMA) having an internal data width, a symbol timing synchronization module configured to receive the parallelized sample stream; and detect therefrom synchronized bit values corresponding to bit values of the received serial data; and a physical convergence sublayer (PCS). The PMA is configured to receive the serial data, deserialize the serial data based on the device-wide clock and internal data width, whereby the received serial data is oversampled, the oversampling of the received serial data being asynchronous relative to a timing of the received serial data, and output a parallelized sample stream. The PCS is configured to receive the synchronized bit values; and delineate packets therefrom to provide packet-delineated parallelized data. The PMA, the symbol timing synchronization module and the PCS are all driven by the device-wide clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.