Semiconductor device with key pattern and electronic system including same
US11889688B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device include; a substrate including a cell array region and a key region, a stack structure on the cell array region including vertically stacked electrodes, a dummy structure on the key region, a vertical channel structure penetrating the stack structure to connect the substrate, a dummy pillar penetrating the first dummy structure, an interlayer dielectric layer on the stack structure and the dummy structure, wherein an upper portion of the interlayer dielectric layer on the dummy structure includes a key pattern that vertically overlaps the dummy pillar, and a capping layer on the key region and covering the key pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.