Array substrates, display panels and display apparatuses
US11889735B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/8731
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an array substrate, a display panel and a display apparatus to avoid influence of a steep slope of a planarization layer on touch performance. The array substrate includes a display region and a mounting hole located in the display region. A side of the mounting hole where a part of a mounting hole blocking column from which a distance of a display region blocking column is less than or equal to 2000 μm is located is denoted as a first side; the array substrate further includes a first metal electrode structure including a plurality of first metal electrodes disposed along a direction perpendicular to the first side, and each of the first metal electrodes includes a plurality of first metal electrode blocks electrically connected with each other in sequence; a size of a first metal electrode block adjoining the first side of the mounting hole expands outwardly in a direction of the first side on a basis of a size of a first metal electrode block not adjoining the first side of the mounting hole. The display panel includes the array substrate. The display apparatus includes the display panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.