Clock synchronization system and operation method thereof capable of synchronizing operation time of internal circuits
US11892871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | May 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.