System-on-a-chip (SoC) based fast path enabler for data applications
US11892948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Mar 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a typical data plane application, there is a packet dispatcher which receives packets from the underlying subsystem for distribution among various threads/processes for further processing. These threads/processes may run on various processing elements (PEs) and pass through multiple stages of processing. As new generation system-on-a-chip (SoC) architectures have multiple heterogeneous clusters with corresponding PEs, packet processing may traverse through multiple PEs in different clusters. Since latencies/performance for different clusters/PEs may be different, packet processing on the SoC may take a variable amount of time, which may lead to unpredictable latencies. The present disclosure provides embodiments to solve the problem of packet processing on heterogeneous clusters/PEs by providing a fast path enabler to the applications for SoC architecture awareness. The fast path enabler understands the cache topology of the SoC and may pre-fetch packets to the desired cache to minimize latencies for improved performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.