Patent · US Active

System and method for bypass memory read request detection

US11892955B2 · kind B2 · utility

0Cited by

29References

20Claims

0Family size

Assignee

MICROCHIP TECHNOLOGY INCORPORATED · US

Inventors

Sanjay Goyal · Roseville, US
Larrie Simon Carr · Kelowna, CA
Patrick Bailey · Port Coquitlam, CA

Key dates

Filing date	May 10, 2022
Grant date	Feb 6, 2024
Priority date	—
Expiry date	Sep 7, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4221
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.