Non-volatile memory programming circuit and a method of programming non-volatile memory devices
US11894061B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/047
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory programming circuit for programming a non-volatile memory device having an array structure includes a plurality of rows, each row having a row index and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: a first source line connected to the top electrode of the memory units comprised at rows of odd row indices, and a second source line connected to the top electrodes of the memory units comprised at rows of even row indices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.