Memory with error checking and correcting unit
US11894089B2 · kind B2 · utility
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14References
18Claims
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Key dates
| Filing date | Sep 22, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jul 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.