Fan-out semiconductor package
US11894310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Apr 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.