Integrated circuit devices
US11894371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jul 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.