Semiconductor package and method for fabricating same
US11894403B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jan 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMacromolecular chemistry, polymers
- WIPO sectorChemistry
Abstract
A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.