Gate-controlled diode and chip
US11894422B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
Abstract
A gate-controlled diode includes a substrate, a gate stacked on the substrate, a gate insulation layer, a first two-dimensional semiconductor layer, a second two-dimensional semiconductor layer, a source, and a drain disposed separately from the source. The gate is embedded in a surface of the substrate, and the gate insulation layer covers the surface of the substrate in which the gate is disposed. The first two-dimensional semiconductor layer is stacked on the gate insulation layer, a portion of the second two-dimensional semiconductor layer is stacked on the gate insulation layer, another portion is stacked on the first two-dimensional semiconductor layer. The another portion of the second two-dimensional semiconductor layer stacked on the first two-dimensional semiconductor layer forms a heterojunction. An orthographic projection of the heterojunction onto the substrate is in an orthographic projection of the gate onto the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.